Performance Analysis of Oversampling Data Recovery Circuit∗
نویسنده
چکیده
In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10−11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis. key words: bit error rate, oversampling data recovery, oversampling ratio, phase jitter, SNR, Markov chain model
منابع مشابه
In-system Jitter Measurement Based on Blind Oversampling Data Recovery
The paper describes a novel method for simple estimation of jitter contained in a received digital signal. The main objective of our research was to enable a noninvasive measurement of data link properties during a regular data transmission. To evaluate the signal quality we estimate amount of jitter contained in the received signal by utilizing internal signals of a data recovery circuit. The ...
متن کاملA 1.0Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method∗
This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was im...
متن کاملA 1.6 Mbps Digital-QAM System for DSL Transmission
An all digital QAM system is studied here for high-speed data transmission on digital subscriber loops. All elements of the system have been fully investigated and their effects on the overall system performance documented. In particular the following issues have been explicitly addressed: utility of an adaptive error-prediction (noise-prediction) filter; equalizer size and convergence; blind e...
متن کاملA CMOS High Speed Data Recovery Circuit
This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two diierent delay taps, the sampler achieves a very ne sampling resolution which is determined by the diierence between the data and clock delays. Thus, the sampler is capable of oversampl...
متن کامل